(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit that includes: output transistors; and an output bonding pad connected to an output signal wire drawn from each of the output transistors, and also relates to a multi-channel semiconductor integrated circuit in which semiconductor integrated circuits are set in an array, each of which serves as a standard cell. The present invention particularly relates to a layout of the semiconductor integrated circuit that performs binary or ternary output, and a layout of the multi-channel semiconductor integrated circuit.
(2) Description of the Related Art
A ternary circuit is conventionally known as a circuit shown in FIG. 7. The ternary circuit shown in this figure includes: a first high-side transistor 4 for high-level output; a second high-side transistor 5 for middle-level output; a back-flow preventing diode 8; a low-side transistor 10 for low-level output; a first level shift circuit 6 that outputs a high-level output control signal; a second level shift circuit 7 that outputs a middle-level output control signal; a pre-driver 9 that controls the first and second level shift circuits 6 and 7 and the low-side transistor 10; a first-high voltage terminal to which a high-level voltage is applied from an exterior; a secondly-high voltage terminal to which a middle-level voltage is applied from the exterior; and an input terminal 19 for respectively providing an output terminal 18 and the pre-driver 9 with a trigger signal.
FIG. 8 is a block diagram showing a structure of a multi-channel semiconductor integrated circuit where the ternary circuit shown in FIG. 7 serves as a standard cell. As shown in this figure, the multi-channel semiconductor integrated circuit consists of plural standard cells and a control logic that controls the standard cells. The control logic controls the pre-driver 9 in each of the standard cells for controlling sequential output from the plural standard cells.
FIG. 5 is a diagram showing a layout of the ternary circuit shown in FIG. 7 on a semiconductor chip. As can be seen in the ternary circuit shown in this figure, the low-side transistor 10, the first high-side transistor 4, the first level shift circuit 6 and the pre-driver 9 are placed in a first row, while an output bonding pad 11, the second high-side transistor 5, the diode 8 and the second level shift circuit 7 are placed and wired in a second row. Components of the ternary circuit are placed in two rows so that a length of each wiring for a flow of a signal inputted and outputted at high-level, middle-level and low-level, becomes almost the same.
FIG. 6 is a layout of a multi-channel semiconductor integrated circuit on the semiconductor chip shown in FIG. 8. The multi-channel semiconductor integrated circuit on the semiconductor chip disclosed in the Japanese Laid-Open Application 3-195045 (see reference to FIG. 3A) is as shown in FIG. 6. In FIG. 6, the ternary circuit shown in FIG. 7 serves as a standard cell, and plural standard cells 26 are vertically aligned in two rows, with each output bonding pad 11 placed on an outer side of semiconductor chip 21. Between the two rows, a timing generation block 15 is placed. The timing generation block 15 is made up of two rows of timing generation unit cells 16, with each row being as many as a number of the standard cells 26.
The timing generation block 15 functions, for example, as a shift register for controlling a timing of a trigger signal to each pre-driver 9 and a timing of an output from each standard cell, according to a control signal outputted from an input control terminal 20. The output from each of the timing generation unit cells 16 is connected, via a bus wiring 36, to the input terminal 19 in a corresponding standard cell 26. In this case, each of the standard cells 26 sequentially outputs a pulse waveform as triggered by a shift operation performed by the timing generation block 15. Also, a surge protection device 37 that forms a path to discharge surge and electrostatic noise in order to protect internal circuits is set in the input control device 20.
According to the layout shown in FIG. 5, the ternary circuit has a two-row structure in which the low-side transistor 10, the first high-side transistor 4, the first level shift circuit 6 and the pre-driver 9 are placed in the first row while the output bonding pad 11, the second high-side transistor 5, the diode 8 and the second level shift circuit 7 are placed in the second row. Therefore, in a case where high-voltage and heavy-current are required as output characteristics of the ternary circuit, a problem is that a planar dimension of a single standard cell that includes the output transistors and level shift circuits gets larger and a size of a free space 38 beneath the pre-driver 9 in the ternary circuit increases, which leads to a decrease in a degree of integration in the circuit.
As for the multi-channel semiconductor integrated circuit shown in FIG. 6, it has recently been demanded that the degree of integration be increased so that one semiconductor chip can include more output channels. In a case of using the ternary circuit shown in FIG. 5 as the standard cell 26, the more the number of the standard cells 26 to be placed in one semiconductor chip increases, the more the planar dimension of the semiconductor chip increases in a vertical direction. However, a width of the timing generation unit cell 16 in the timing generation block 15 that drives a standard cell 26 is smaller than a width of the standard cell 26. Therefore, in a case of applying the conventional layout as shown in FIG. 6 to the standard cell 26 and the timing generation block 15 in the multi-channel semiconductor integrated circuit, a large unnecessary free space 38 is generated beneath the timing generation block 15 within the semiconductor integrated circuit, as a result. This decreases the degree of integration in the semiconductor integrated circuit.
Due to a difference in a length of the bus wiring 36, which is laid between the timing generation unit cell 16 and the pre-driver 9 in each standard cell 26, the length of the bus wiring 36 gets longer as a degree of integration gets higher, and a wiring capacitance and a delay time in transferring a signal increase accordingly. As a result, unbalance is generated among output characteristics (delay time in particular) of the ternary circuits depending on the length of the bus wiring 36 that connects the timing generation unit cell 16 and the pre-driver 9.